The driving force behind the increasing demand of low dropout regulators (LDO) stems from the requirement of efficient power management in battery operated portable consumer products for their low power operations. The fundamental design challenge in an LDO is to stabilize it over a zero load current (no load) to a maximum load current (full load) required for a particular application. In addition to stability, various other performance parameters of the LDO also turn to be critical depending on a particular application, where it is being incorporated. LDO supplying current to low voltage sub-100 nm channel length load circuitry must have a very good transient response, more specifically the transient voltage peak and trough in a controlled output of the LDO should not exceed a certain voltage range both during dynamic load current step and large current spike inherent to digital load circuitry for safe operations of the load circuitry. More over, the stability must be ascertained for both kinds of loading effect offered by the load circuitry. Loading effect of analog circuits is closer to a current sink type load, whereas of digital circuits it is closer to a resistive type load. In reality, the LDO sees at its output the combination of resistive as well as the current sink type load.
FIG. 1 describes a block diagram of a conventional LDO 100 according to a prior art 1. The LDO 100 includes an error amplifier 110, a voltage buffer 120, a PMOS driver transistor 130 and a feedback network comprising with resistors R1 (101) and R2 (102). The load to the LDO 100 is modeled with a resistive load RL (105) in parallel with a current sink load IL (106). An off-chip decoupling capacitor CL (103) is connected to an output of the regulator 100 for dominant pole frequency (equation 1.1A) compensation. A bond inductance LB (107) associated with the bond wire connecting the internal output (node 108) of the regulator 100 to the external positive terminal (node 109) of the off-chip decoupling capacitor CL (103) can also be considered in the high frequency response of LDO. A load current from the output (node 108) of the regulator 100 can be drawn internally (from node 108 itself) or it can be routed externally from output pin (node 109), where an external decoupling capacitor is connected and fed back to the chip through other core-supply pins (when provided in the chip). Accordingly, positions of the IL (106) and RL (105) change to node 108 in FIG. 1. A small series resistance in series with the bond inductance 107 can also be considered.
The dominant pole frequency for prior art 1 can be approximated by
                              P          1                =                              -                          G              O                                            C            L                                              (                  1.1          ⁢          A                )            where Go is the total conductance at the output node 108 of LDO 100 andGO=GDS2+GFB+GL where, GDS2 is the output conductance of the PMOS driver transistor 130,
            G      FB        =          1                        R          1                +                  R          2                      And            G      L        =          1              R        L            
For a current sink type load GL can be neglected and for most of the load current range GO is decided by GDS2, which can be approximated byGDS2=λ×(IL+ISINK)≈λ×IL  (1.1B)where IL is the load current (106) and ISINK is the bleed current flowing through the feedback resistor (R1+R2), which is generally negligible compared to IL in low power LDO regulators.
Therefore, for current sink type load the dominant load pole for prior art 1 can be represented by
                              P          1                ≅                                            -              λ                        ×                          I              L                                            C            L                                              (                  1.1          ⁢          C                )            
For a resistive load equation 1.1C also includes GL as given below:
                              P          1                ≅                              -                          (                                                λ                  ×                                      I                    L                                                  +                                  G                  L                                            )                                            C            L                                              (                  1.1          ⁢          D                )            
The non-ideality in the off-chip capacitor CL (103) is modeled with a series resistance RESR (104), which is called an Equivalent Series Resistance (ESR). The ESR (104) generates a zero in the loop transfer function at a frequency that can be approximated by
                              Z          ESR                ≅                              -            1                                              R              ESR                        ×                          C              L                                                          (        1.2        )            
The second pole for prior art 1 occurs at the output node 112 of the voltage buffer 120 and can be approximated by
                              P          2                =                              -                          G                              O                ⁢                                                                  ⁢                2                                                          C            par                                              (        1.3        )            where GO2 is an output conductance of the voltage buffer 120 and Cpar is the total capacitance at node 112, which is mainly contributed from the gate capacitance of the large PMOS driver transistor 130.
Stereotypically, the ESR zero (ZESR in equation 1.2) is utilized to cancel out the effect of second pole P2 (equation 1.3) and thus a good stability margin is achieved for prior art 1.
A third pole in the loop transfer function of prior art 1 generally occurs at an output node 111 of the error amplifier 110 and can be given by
                              P          3                =                              -                          G              01                                            C            01                                              (                  1.4          ⁢          A                )            where G01 is the output conductance of the error amplifier 110 and C01 is the total node capacitance at node 111, whose main contribution comes from the gate capacitance of the input MOS (metal-oxide) transistor of the voltage buffer 120.
In addition, there is a fourth pole (P4), which is originated from the total bypass capacitance of node 108 (this capacitance comes from the chip capacitance when node 108 internally drives the load circuitry and routing capacitance) except CL (103) and ESR of external decoupling capacitor CL (103) which can be approximated by
                              P          4                ≅                  1                      ESR            ×                          C              B                                                          (                  1.4          ⁢          B                )            
The above pole P3 (equation 1.4A) and P4 (equation 1.4B) (are called parasitic poles for prior art 1. For designs with high ESR the second pole is given by equation 1.4B and the third pole from equation 1.3, but it does not modify the compensation method and the number of poles in the system remains same.
The philosophy of the compensation method utilized in prior art 1 is to select a load capacitor CL (103) too large to include these parasitic poles P3 (equation 1.4A) and P4 (equation 1.4B) within the unity gain frequency (equation 1.6) even at the highest load current drawn from the LDO.
Loop gain for prior art 1 for a unity feed back factor is given by
                              Gain          loop                =                                            G              mi                        ×                          G              mp                                                          G              01                        ×                          G              O                                                          (        1.5        )            and a loop gain bandwidth or the unity gain frequency (UGF) for prior art 1 is given by
                              f          T                =                                            Gain              loop                        ×                          p              1                                =                                                    G                mi                            ×                              G                mp                                                                    G                01                            ×                              C                L                                                                        (        1.6        )            where, Gmi, Gmp are transconductances of the error amplifier (110) and the driver transistor (130).
Large value of CL (103) reduces the bandwidth (equation 1.6) of prior art 1, which increase a transient response time of the LDO 100. However, the load capacitor CL (103) can be made large enough to supply or sink the instantaneous transient load current spikes without much affecting the controlled output. The most crucial drawback of prior art 1 arises from the fact that the LDO stability is critically dependent on an ESR value, which largely depends not only on a manufacturer of the capacitor, but also varies with an operating frequency and temperature and thus creates stability problem in actual scenarios.
In addition, the recent trend in a system integration demands system on chip (SoC) solution, which left the designers with either a capacitor free on-chip LDO or an LDO with very small surface mount (SM) type external decoupling capacitor to minimize the transient voltage peaks and troughs in a controlled output voltage of the regulator. Compared to normal leaded resistors and capacitors, the SM counterparts take much smaller area, which can be very easily incorporated into the SoC integration.
Load capacitor of external decoupling capacitor free LDO consists of the total chip capacitance it drives. The chip capacitance includes the equivalent gate capacitance of the load circuitry and the big n-well capacitance (a substrate of a PMOS load transistor and other n-wells connected to a regulated supply), and other parasitic capacitance (routing capacitor etc). Moreover, few on-chip decoupling capacitors may also be connected to the output of the regulator for better transient response of the LDO. Therefore, the load capacitor value provided to the designers for an LDO in SoC application is generally varies from a few nano-Farads to a few hundreds of nano-Farad depending on the application. Henceforth, the LDO having a load capacitor value in the above mentioned range is called as a low-load-capacitor LDO.
Stability is to be achieved for the low-load-capacitor LDO without compromising the other performance parameters of the LDO.
A small value of the load capacitor CL (103) in low-load-capacitor LDO proportionally increases the dominant load pole frequency P1 (equation 1.1A) and the unity gain frequency (equation 1.6). At a full load current, the second pole P2 (equation 1.3) protrudes into the unity gain frequency (UGF, equation 1.6) and degrades the stability when frequency compensation method of prior art 1 is applied in case of the low-load-capacitor regulator compensation.
Additionally, a low value of the load capacitor CL (103) introduces a wide variation in the dominant load pole P1 due to a change in load current IL (equation 1.1C and 1.1D) and at a maximum load current the dominant load pole P1 increases to such a high frequency that, in addition to P2, the parasitic pole P3 or P4 (equation 1.4A or 1.4B) occurs very near to the UGF or may fall within the UGF (equation 1.6) and stability margin of the LDO (100) becomes very low at the higher load current range for prior art 1.
Moreover, the ESR (104) of an on-chip capacitor is too small (comes from routing and via resistance) to consider and for a small SM type external decoupling capacitors its value falls in such a low range that ESR zero ZESR (equation 1.2) lies at much higher frequency than the UGF (equation 1.6), which can't be exploited for cancellation of second pole P2 (equation 1.3) as is done for prior art 1. So, the compensation strategy adopted in prior art 1 no longer holds good for the low-load-capacitor regulators suitable for the SoC applications.
New compensation methods for the low-load-capacitor LDO are urgently required to keep pace with the current SoC trends. The compensation strategy must be such that the regulator consumes low power, and provides a good phase margin over zero to full load current range (for good transient response over the full load current range) using a load capacitor in the range of a few nano-Farads to a few hundreds of nano-Farads.
FIG. 2 describes a block diagram for a LDO 200 according to U.S. Pat. No. 6,603,292 (prior art 2) Prior art 2 includes a load capacitor (203) with a value of 470 nano-Farad and an adaptive zero frequency circuit is incorporated to achieve a stability for a limited load current range for the LDO 200.
In prior art 2, a dominant pole P1 is realized at the regulator's (200) output node 208 and has the similar expressions as given by equations 1.1A to 1.1D.
An adaptive zero ZC, is introduced within its unity gain frequency in the loop transfer function, which can be approximated by
                              Z          C                =                              -            1                                              R              DS                        ×                          C              C                                                          (        2.1        )            where RDS is a drain-source ac resistance of an NMOS transistor 216 and CC is the compensation capacitor 217.
The ESR zero has been neglected in prior art 2 as it uses 470 nano-Farad ceramic capacitor (203) with a low ESR (204) of nearly 10 mΩ, which produces a very high frequency ESR zero (nearly 3.3×107 Hz).
In addition to ZC (equation 2.1), a pole is also created at node 219 and its frequency can be approximated by
                              P          par                =                              -                          (                                                C                  c                                +                                  C                  par                                            )                                                          R              DS                        ×                          C              c                        ×                          C              par                                                          (        2.2        )            where Cpar is the parasitic capacitance at the node 219 except CC and is mainly contributed from an input capacitance of the voltage buffer 210. When the value of Cpar is not much less than CC (217), then the zero ZC (equation 2.1) is cancelled by the pole Ppar (equation 2.2) itself and ZC can't be utilized in the stability compensation effectively.
Additionally, node 218 of the LDO 200 contributes another pole approximately at
                              P          par          ′                =                              -                          G                              O                .                BUFF                                                          C            par            ′                                              (        2.3        )            where GO.BUFF is an output conductance of the voltage buffer 210 and C′par is the total parasitic capacitance at the node 218, which is mainly contributed from the gate capacitance of the large PMOS driver transistor 220.
Another pole originates according to equation 1.4B (though it can be neglected as ESR is very low) and implies that the LDO 200 has also to be considered with respect to these four poles.
It is observed in prior art 2, that the ZC (equation 2.1) stops the −20 dB/decade gain fall due to P1 (equation 1.1A), and the residual gain falls below a unity gain with the help of one of these two poles (may be P′par from equation 2.3 with the assumption P′par<Ppar) or may be with the help of the other parasitic pole too (Ppar, equation 2.2) depending on the amount of residual gain and the separation between these parasitic poles (P′par & Ppar) occurring at node 218 and 219 of the LDO 200. When these parasitic poles (2.2 and 2.3) are not very far away from each other, then they produce a local phase dip with a poor phase margin for the LDO 200 in case of the compensation method of prior art 2.
More over, as the maximum consumption limits the maximum reflection current through the NMOS transistor 215 at a full load condition, therefore at a small load current the reflection current through the NMOS transistor 215 becomes very small which increases the RDS of the NMOS transistor 216 to a very high value and correspondingly decreases the adaptive zero frequency (ZC in equation 2.1), which can be small enough to create a stability problem due to an early gain halt. The result shows that a phase margin with a load resistance 280 KΩ is only 22° at 7 dB open-loop gain and few degrees at a unity gain frequency. This small phase margin makes the transient response oscillatory in nature and demands a long settling time. Additionally, a smaller phase margin produces a bigger transient peak, which may cross a maximum voltage limit for the safe operation of the load circuits.
In addition, as the LDO 200 includes an external load capacitor (203) (of 470 nano-Farad capacitance value) and compensated with dominant load pole (P1, equation 1.1A) frequency compensation, therefore the unity gain frequency at maximum load current becomes of the order of several MHz. When a bond inductance 207 (which is several nano-henries and largely depends on the package used for a particular application) is included, the stability of the LDO 200 having a large bandwidth (several MHz) may be severely affected. This inductance introduces an additional zero on the top of a loop transfer function, which is not very far away from UGF of an LDO having a very high bandwidth. This extra zero further enhances the unity gain frequency and degrades the phase margin. The additional zero frequency can be dampened out by adding extra bypass capacitors. But this introduces a pair of closely-spaced complex poles, which creates a resonant notch in the magnitude as well as phase response curve of an LDO. Although the phase margin may be slightly improved, the response becomes unstable as it is on the edge of a very sharply changing phase response. This problem is removed for the LDO using a large external decoupling capacitor with bigger ESR, which limits the bandwidth of LDO to few MHz and ESR increases the damping of the LC tank circuit too. In case of prior art 2, the bandwidth continues to increase with increasing load current due to an increase in the dominant load pole P1 frequency (equation 1.1C & 1.1D).
The problem can be solved if the frequency compensation can be achieved by means of any internal node dominant pole rather than the dominant load pole at the output of the LDO 200. In that case the dominant internal pole frequency variation must be much lesser with the load current variation and second pole of the LDO 200 may be cancelled with a zero realized in the transfer function. Added advantage can be gained if the zero can track the variation in the second pole with a load current.
FIG. 3 describes the block diagram of an LDO 300 according to U.S. Patent Application Publication No. 20050127885 (prior art 3). Prior art 3 proposes another method for realizing an on-chip LDO (300) with a load capacitor CL (303) (of approximately 1.225 nano-Farad) due to a load circuitry, which the LDO 300 is driving.
The open loop transfer function for LDO 300 can be expressed as follow
                                                        V              out                        ⁡                          (              S              )                                                          V              in                        ⁡                          (              S              )                                      =                                            -                              G                mI                                      ⁢                          G              mII                        ⁢                          R              I                        ⁢                                          R                II                            ⁡                              (                                                      R                    Z                                    +                                      SC                    C                                                  )                                                                        (                              1                +                mS                            )                        ⁢                          (                              1                +                pS                +                                  qS                  2                                            )                                                          (        3.1        )            where GmI, GmII; RI, RII, and RZ are the transconductance of an error amplifier 312 and transconductance of a driver PMOS transistor 310; an output impedance of the error amplifier 312, impedance at node 308 and the output impedance of the voltage buffer 350, respectively. CC is the compensation capacitor 306.
The coefficients p and q of the second factor in the denominator of equation 3.1 can be expressed as
                              p          =                      (                                          1                                  P                  2                                            +                              1                                  P                  3                                                      )                          ⁢                                  ⁢        and        ⁢                                  ⁢                  q          =                      1                                          P                2                            ⁢                              P                3                                                                        (        3.2        )            where P2 & P3 in equation 3.2 are second and third poles in the loop transfer function 3.1, respectively.
The dominant pole occurs at node 311 due to a miller multiplication of the capacitor CC (306) across a second gain stage, which is the PMOS driver transistor 310, and the dominant pole frequency can be approximated by
                              P          1                =                                            -              1                        m                    ≅                                    -              1                                                      R                I                            ×                              (                                                      G                    mII                                    ⁢                                      R                    II                                    ×                                      C                    C                                                  )                                                                        (        3.3        )            
The transfer function in 3.1 has a left half S-plane zero approximately at
                              Z          C                =                              -            1                                              R              Z                        ⁢                          C              C                                                          (        3.4        )            where, RZ, is the output impedance of the source follower 350.
The second factor in the denominator of equation 3.1, which contributes two poles in the open-loop transfer function, has a damping factor given by
                    ξ        =                              1            2                    ×                                                    (                                                      C                    L                                                        C                    I                                                  )                            ×                              1                                                      G                    mII                                    ⁢                                      R                    Z                                                                                                          (        3.5        )            where GmII is a transconductance of the PMOS driver transistor 310 and is proportional to the square root of the load current IL (305), assuming the drain current of the PMOS driver transistor 310 is mainly contributed by the load current IL (305). The CL (303) is the load capacitance at node 308 and CI is the total node capacitance at node 311 except CC. CI is mainly contributed from a gate capacitance of the large PMOS driver transistor 310. Except GmII other variables in equation 3.5 are independent of the load current IL (305). So, the damping factor can be expressed as
                    ξ        ∝                  1                                    I              L                        4                                              (        3.6        )            
P2 and P3 in the LDO 300 becomes real at low load current (IL) range when the damping factor (equation 3.5 & 3.6) is greater than one and their frequencies can be approximated by
                              P          2                =                              -                          G              mII                                            C            L                                              (        3.7        )                                          P          3                =                              -            1                                              R              Z                        ⁢                          C              I                                                          (        3.8        )            
With the increase in load current IL (305), when the value of the damping factor (equation 3.5) becomes less than one then these two poles form a pair of complex conjugate poles. Equation 3.7 states that with the increase of load current the lower frequency pole P2 continuously increases due to square root proportionality of GmII with load current IL (305) and higher frequency pole P3 (equation 3.8) decreases with load current IL (305) as gate capacitance of 310 increases (increasing CI in equation 3.8) with increasing load current. At higher load current when damping factor (equation 3.5) becomes less than one, the second and third poles combine and form a pair of complex conjugate pole. In prior art 3 the values of the CC and the CI are such that this complex pole pair generally occurs after the zero ZC (equation 3.4) at higher load current range.
When the zero ZC (equation 3.4) protrudes into the UGF, then −20 dB/decade fall in the gain by P1 (equation 3.3, this dominant pole is not at very low frequency due to limited value of on-chip CC and moderate gain of the driver) is stopped and residual gain is diminished with the help of this complex pole pair as shown in FIG. 9 through the simulated Bode plot of prior art3 (with a resistance in series with CC 306 as explained latter on). Phase margin is degraded due to a sharp change in the phase from a complex pole pair and results in a damped oscillation in the transient settling response.
The natural frequency for the complex conjugate pole pair is given by
                              P          n                =                              G            mII                                              C              L                        ⁢                          R              Z                        ⁢                          C              I                                                          (        3.10        )            
In prior art 3 these complex poles are obtained at higher frequency (equation 3.10) when a very small load capacitor is considered (CL in prior 3 is 1.225 nano-Farad). Also the zero ZC (equation 3.4) in prior art 3 is much greater than the unity gain frequency due to a small value of RZ. Hence given to above condition of very low load capacitor value prior art 3 shows a good phase margin.
Unfortunately, as previously pointed out that lower the load capacitor value, larger is the voltage peak and trough during the quick transient load current change. LDO required to have infinitely high bandwidth to respond to these instantaneous load current spikes which is not possible for a stable LDO. When transient trough becomes less than the lower limit of controlled output voltage it may hamper the operation of the load circuitry temporarily, but if the transient voltage peak crosses the safe operating area (SOA) of load circuitry it can burst out the gates of the load circuits and may be responsible for permanent failure of the chip.
To avoid this fatal trouble we conventionally add a few on-chip decoupling capacitors (if possible small SM type off-chip decoupling capacitor is also added when off-chip area constraint does not allow large sized external capacitors) and do not depend only on the default chip capacitance to smoothen out this transient peak and trough. Accordingly, when load capacitor CL (303) becomes several tens to hundreds of nano-Farads, the complex pole pair frequency falls within UGF at higher load current degrading the phase margin badly due to sharp phase change offered by the complex pole pair.
In addition, the phase margin at low load current also deteriorates as shown in FIG. 10 (figure titled as prior art 3 without RC). This is due to the fact that a second pole frequency P2 (equation 3.7, when P2 and P3 becomes real) decreases with the decreasing load current (as GmII in equation 3.7∝√{square root over (IL)}) and falls within the UGF at low load current range for a considerable load capacitance CL (303) required for a safe transient behavior. The power management in battery operated portable consumer products includes a standby mode of operation when the full activity of the chip is not required. During this standby mode, current requirement of the chip is minimal and its value varies from hundreds of microampere to a few milliamperes depending on the application. So, prior art 3 topology does not hold good in this low consumption mode operation when an LDO has to supply a small load current.
The phase margin at a low current range can be improved, for prior art 3, by inserting a resistor (RC) in series with the capacitor CC (306). In this case, RZ in equation 3.4 is increased by this added series resistance (RC) and thus the zero frequency ZC (equation 3.4) can be decreased to lower frequency to improve the phase margin at low load current range. Unfortunately, an increase in the value of RZ decreases the complex pole frequency (equation 3.10) as well and thus the phase margin at a higher load current range is degraded as shown in the FIG. 10 (figure titled as prior art 3 with RC in series with CC).
Phase margin at a low load current range in prior art 3 can also be improved by further increasing the value of the on-chip compensation capacitor CC (306) to lower the dominant pole frequency P1 (equation 3.3), so that the gain falls below unity solely with the help of this dominant pole P1 before the second load P2 (equation 3.7) pole occurs. But, it demands a fairly large value for the compensation capacitor CC (306) and hence a large chip area.
On the other hand, a constant sink current can be drawn from the PMOS driver 310, so that even at no load current the second pole frequency P2 (equation 3.7) occurs after UGB and at least 45° phase margin can be obtained at no load condition. But this constant sink current is added to the consumption of the LDO 300, which is specifically needed to be consumed in the low load current region, which increases the consumption in the standby operation.
Finally, when an input supply 313 is much greater than the regulated output voltage of the LDO 300, the variable capacitor 306 never leaves the accumulation region and variation in the capacitance of CC (306) with a load current (IL) becomes negligible. On the other hand, when the input supply 313 is near to the output voltage (maintaining only the dropout voltage) of the LDO 300, the capacitor CC (306) always operates in the depletion region and thus similar variation in the capacitance of the voltage dependence capacitor CC (306) with the load current is not be obtained for varying input power supply (313) range.
The damping factor (equation 3.5) of the above mentioned complex pole pair can be controlled by a damping factor control (DFC) block and the complex pole pair can be cancelled with the help of two zeros according to U.S. Patent Application Publication No. 20040164789. One zero is associated with the ESR of the off-chip capacitor and another one realized from the lead compensator in the feedback network. Although for low-load-capacitor LDO with negligible ESR and LDO having controlled output voltage near to reference voltage (for sub-100 nm low voltage CMOS circuits), one cannot utilize these two zeros efficiently for pole-zero cancellation and problem persists. Additionally, designer has to meet stringent mathematical equalities, which may not be achievable in all process corners. Also the complex poles due to load capacitance are ignored in case of an on-chip LDO. Stability at no load for the on-chip LDO is achieved by drawing a constant sink current from the PMOS driver transistor. As already mentioned, this method of sinking a constant load current to achieve stability at no load is not a good low power solution.
Thus, there is an urgent need for a robust LDO compensation technique, which works equally fine for a load capacitor ranging from a few nano-Farads to a few hundreds of nano-Farads and provides fairly good phase margin over no load to a certain maximum load current with low power consumption. More over, added advantage can be obtained if the performance of the compensation circuits does not critically dependent on satisfying some rigorous mathematical equality which may not be achievable in all the process corners and other performance parameters of the LDO should not be critically affected.